A typical analog video signal 11 for driving an analog video display is illustrated in FIG. 1. As shown in FIG. 1, the analog video signal 11 is a composite signal having lines of analog data 12 combined with other sweep and synchronization (sync) signals, which include a blank level 14, having a front porch 14a and a back porch 14b, and a sync level 16. A blank period is defined as including the front porch 14a, the sync level 16, and the back porch 14b, and a sync period is defined as the time period in which the analog video signal 11 exhibits the sync level 16. The front porch 14a essentially cues the electron beam associated with a raster display to turn off when the beam sweeps from the end of a scan line to the beginning of the next scan line. The sync level 16 cues the electron beam to change either a scan line or a frame, depending upon its time period, and/or resets counters and other support circuitry. When the sync level 16 cues a scan line, then it is referred to as a "horizontal sync" (Hsync). When the sync level 16 cues a frame, i.e., when it exhibits an extended time period, then it is referred to as a "vertical sync" (Vsync). Furthermore, the back porch 14b permits initialization of the electron beam and other support circuitry prior to acting upon a new scan line or frame.
If the analog video display is multicolor, then there would generally be one of the analog video signals 11 allocated to each color, such as for red, green, and blue. However, only one of the analog video signals, for instance, the one allocated to green, usually has the sync levels 16.
Recently, there has been a trend in the industry toward developing video displays which are driven by digital video signals as opposed to analog video signals. An example of such a digital video display is the model LQ12D011 TFT LCD flat panel display manufactured and made commercially available by the Sharp Corporation, Japan. Thus, it has recently been desirable to convert the analog video signal 11 of FIG. 1 into a digital video signal for driving a digitally-controlled display. This process can be described graphically with reference to FIG. 1. Referring to FIG. 1, in the process of converting the analog video signal 11 into a digital video signal, the analog data 12 is converted to a series of digital codes, depending upon its amplitude at a given point in time. For Sharp's digital display device, the analog data 12, which typically represents 256 different intensity levels for a particular color, must be converted to only 8 intensity levels, as is represented in FIG. 1 by levels 0 through 7. The lowest possible color intensity level is commonly referred to as the "black" level, whereas the highest possible color intensity level is commonly referred to as the "white" level,
In order to properly convert the analog video signal 11 to a digital video signal comprising a series of digital codes, it is necessary to generate a sync signal for indicating when the analog video 11 exhibits the sync levels 16. A typical sync separation system 21 is illustrated in FIG. 2. A sync separation system, similar to that shown in FIG. 2, can be implemented with the model CXA1365S sync discriminator for a CRT (cathode ray tube) display manufactured and made commercially available by the Sony Corporation, Japan.
As illustrated in FIG. 2, the sync separation system 21 sometimes has a capacitor C1 for shifting the voltage swing of the incoming analog video signal 11 by a predetermined offset. The capacitor C1 is connected to the noninverting terminal (+) of a voltage comparator 24, which compares the shifted analog video signal at the noninverting terminal 23 with a reference voltage V.sub.REF at the inverting terminal 26 (-) of the comparator 24. The reference voltage V.sub.REF is often generated with a voltage divider 28 comprised of resisters R1, R2 for dividing the supply voltage V.sub.S. A clamp circuit 31 ensures that the shifted analog video signal at the noninverting terminal 23 does not descend below a predetermined voltage amplitude. The clamp circuit 31 comprises a voltage divider 32 having resisters R3, R4 for establishing a voltage across a diode D1, which is connected to the noninverting terminal 23. If the voltage on terminal 23 begins to drop below the predetermined voltage amplitude, the clamp circuit 31 will introduce current i.sub.0 into the analog video signal 11 to thereby maintain the voltage level at terminal 23 above the predetermined voltage amplitude. Furthermore, the sync separation system 21 is usually compatible with transistor-transistor logic (TTL), and therefore, the supply voltage V.sub.S is usually set at about +5 volts, and the sync separation system 21 is usually equipped with a resistor R5 for pulling the output of the voltage comparator 24 to and from industry recognized TTL voltage levels.
In general, the precision of the sync separation system 21 in comparing the shifted analog video signal at the noninverting terminal 23 with the reference voltage V.sub.REF at the inverting terminal 26 is not optimum and manifests itself as a horizontal shift in the sync signal output on connection 34 from the comparator 24. One reason for the imprecision is that the comparator 24 introduces a certain amount of propagation uncertainty, or uncertainty of the propagation delay. Another reason is that the current i.sub.0 from the clamp circuit 31 and the reference voltage V.sub.REF are generated and controlled independently, and therefore, the signals at terminals 23, 26, which are compared by the comparator 24, exhibit inconsistent propagation delays which leads to an inaccurate comparison by the comparator 24. In the sync separation system 21 of FIG. 2, a typical propagation uncertainty is about 60 to 100 nanoseconds (10.sup.-9 seconds).
Despite the propagation uncertainty, the sync separation system 21 is useful with CRT displays, because CRT displays can easily accommodate for any slight horizontal shift associated with the sync signal on output connection 34. As long as the sync separation system 21 has a constant total propagation uncertainty from frame-to-framer a CRT display generally has no problem accurately displaying the data.
However, although the prior art sync separation systems are useful in separating out sync levels for CRT displays, the prior art sync separation systems are not useful in a high frequency sync separation system for an analog-to-digital interface. This is because the analog-to-digital conversion generates a dot clock signal and synchronizes it with the output 34 of the sync separation system 21. Moreover, the propagation uncertainty associated with the sync signal must be far less than the time period allocated to each picture element (pixel) by the dot clock signal. However, at high frequency, the pixel time window becomes very small. For example, at 84.5 million pixels per second, the pixel time window is approximately 11.82 nanoseconds. Accordingly, a high frequency analog-to-digital interface cannot tolerate the propagation uncertainties (60 to 100 nanoseconds) associated with prior art sync separation systems, including that which is shown in FIG. 2.